/**
 * Test bench for reg_file.v
 **/

module tb;
   parameter DATA_WIDTH = 32;
   parameter ADDRESS_WIDTH = 5;

   reg clk, wen;
   reg one;
   reg al;
   reg [ADDRESS_WIDTH-1:0] raddr1, raddr2, waddr;
   wire [DATA_WIDTH-1:0] out1, out2;
   reg [DATA_WIDTH-1:0]     in;
   reg                      reset;
   integer                  i;
   Reg_file #(.DATA_WIDTH(DATA_WIDTH), .REGFILE_WIDTH(ADDRESS_WIDTH))
   regs(.clk(clk), .wen(wen), .raddr1(raddr1),
        .raddr2(raddr2), .waddr(waddr),
        .out1(out1), .out2(out2), .in(in), .reset(reset));


   initial begin
      $dumpfile("test_reg_file.vcd");
      $dumpvars(0, tb);
      $dumpvars(0, regs.mem[1]);
   end

   initial begin

   end

   initial begin
      clk = 0;
      forever #1 clk = ~clk;
   end

   initial begin
      $monitor ("TIME = %g, out1 = %d, out2 = %d, clk = %d",
                $time, out1, out2, clk);
      reset = 1;
      #2 reset = 0;
      // check reset result.
      @ (posedge clk) ;
      for (i = 0; i < 1 << (ADDRESS_WIDTH-1); i = i+1) begin
         raddr1 = i;
         raddr2 = (1 << (ADDRESS_WIDTH-1)) - i - 1;
         @ (posedge clk) ;
      end
      // test write
      @ (negedge clk);
      wen = 1;
      for (i = 0; i < 1 << (ADDRESS_WIDTH-1); i = i+1) begin
         raddr1 = i;
         raddr2 = i;
         waddr = i;
         in = 32 - i;
         @ (negedge clk);
      end
      // disable write
      wen = 0;
      for (i = 0; i < 1 << (ADDRESS_WIDTH-1); i = i+1) begin
         raddr1 = i;
         raddr2 = i;
         waddr = i;
         in = i;
         @ (negedge clk);
      end
      #2 $finish;
   end // initial begin

endmodule
